It is known that semiconductor memory devices comprises a matrix of memory cells arranged in rows (word lines) and columns (bit lines).
It is also known that semiconductor memory devices conventionally incorporate row and column redundancy circuits for increasing the manufacturing process yield.
A row redundancy circuit is a circuit that detects if a current address supplied to the memory device corresponds to a defective row of the memory matrix containing one or more defective memory cells and, if so, selects a redundancy row of redundancy memory cells instead of the defective row.
Similarly, a column redundancy circuit is a circuit to detect whether the current address supplied to the memory device corresponds to a defective column of the memory matrix containing one or more defective memory cells and, if so, selects a redundancy column of redundancy memory cells in substitution of the defective column.
Normally, a certain number of redundancy rows and redundancy columns are provided in the memory device, said number depending on the defectiveness of the manufacturing process. The row redundancy circuit and the column redundancy comprise non-volatile memory registers (redundancy registers) each one capable of storing an address of a defective row or column and controlling the selection of an associated redundancy row or column when the current address supplied to the memory device coincides with one of said defective addresses. The provision of row and column redundancy circuits has a cost in term of chip area, the latter increasing with the increase of the number of redundancy memory elements provided in the memory device.
Some of the signals generated by the row and column redundancy circuits must be routed through the memory device chip. For example, for test purposes it may be useful to know how many and which redundancy rows and redundancy columns have been used to replace defective rows and columns. More particularly, it is important to have the maximum visibility of the redundancy circuits, for example when it is to be decided which redundancy registers are to be used to store defective addresses, during the debugging phase of the memory device, during reliability tests, for obtaining statistics of the defectiveness of the manufacturing process, for optimizing the number of redundancy memory elements to be provided, and for inspections after delivery of sold products. Conventionally, this requires routing redundancy row and column selection signals generated by the redundancy registers to the output terminals of the memory device chip.
The necessity to have many dedicated signal lines running through the chip is disadvantageous, especially in memory devices of large size, because the chip area increases and the benefit in term of yield of the manufacturing process is reduced.